Dual processor framer
US7245725B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 2002 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Dec 3, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual processor framer includes a receiver and a transmitter which share common circuitry and/or code. Separate direct memory access controllers may be used for each of the receiver and transmitter. Processing is distributed over two or more processors. One processor may be a lower power processor while another processor may be a higher power processor. At least one of the two or more processors may be programmable or reconfigurable. The transceiver is configured to provide internal loop back self testing at various points in the processing. Timing within the transceiver may be established almost entirely by a single clock domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.