Power optimization of a mixed-signal system on an integrated circuit
US7246027B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2005 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Mar 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for conserving power of a mixed-signal system-on-a-chip having analog circuitry, involving determination of an analog variation parameter that is representative of an integrated circuit fabrication process variance of the integrated circuit, and an operational temperature associated with the analog variation parameter. With the analog variation parameter and the operational temperature, an adjustment signal is determined for a power supply level of the integrated circuit, such that power consumption of the integrated circuit is optimized. Further, in mixed-signal integrated circuits with digital and analog circuitry, a digital variation parameter is determined, where the adjustment signal determination is based on the digital variation parameter and the analog variation parameter with respect to the operational temperature. With such a method and apparatus, power consumption is optimized on an IC-by-IC basis such that power consumption of each IC is optimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.