Bus master and bus slave simulation using function manager and thread manager
US7246052B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2002 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Jul 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The system simulator comprises master simulators 1f, 1s, 2f and 2s for simulating a bus master, a slave simulator L for simulating a bus slave, a function manager F for sequentially actuating the master simulator and the slave simulator by using a function call and a thread manager S for actuating the master simulator by using a thread switching. When the master simulator activated by using the function call from the function manager accesses the slave simulator and an access blocking is caused, the master simulator controls the thread manager such that the master simulator is activated by using the thread switching carried out by the thread manager. Thus, it is possible to carry out the simulation at a high speed without getting into a dead lock state caused by the access blocking and without changing the simulator for simulating a conventional bus master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.