Queuing cache for vectors with elements in predictable order
US7246203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2004 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Nov 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache for storing data elements is disclosed. The cache includes a cache memory having one or more lines and one or more cache line counters, each associated with a line of the cache memory. In operation, a cache line counter of the one or more of cache line counters is incremented when a request is received to prefetch a data element into the cache memory and is decremented when the data element is consumed. Optionally, one or more reference queues may be used to store the locations of data elements in the cache memory. In one embodiment, data cannot be evicted from cache lines unless the associated cache line counters indicate that the prefetched data has been consumed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.