Systems for increasing register addressing space in instruction-width limited processors
US7246218B2 · kind B2 · utility
1Cited by
5References
10Claims
0Family size
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Key dates
| Filing date | Nov 1, 2004 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | May 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file, which are communicatively coupled to each other and arranged to accommodate shortened instruction words in multiple-issue processors. These components are arranged to permit greater access to registers by instructions, thereby permitting reduction of the word length, as compared to conventional very long instruction word (VLIW) processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.