Method and apparatus for estimating random jitter (RJ) and deterministic jitter (DJ) from bit error rate (BER)
US7246274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2004 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Jan 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3171
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus and method provides prediction of BER for an interface between ICs, such as a processor and a memory device, without using special test equipment. A known data pattern or PRBS is transmitted to a receiver, which compares the received data values with expected data values to determine if a bit error has occurred in an embodiment of the present invention. A center of data eye and the edge of the data eye are sampled (over sampled) in order to determine if a bit error has occurred in an alternate embodiment of the present invention. A first counter is used to count the total number of bits sampled and the second counter is used to count the number of errors that occurred in the total number of bits sampled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.