Memory integrity self checking in VT/TU cross-connect
US7246289B2 · kind B2 · utility
0Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2003 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Nov 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for detecting errors in a memory includes generating a first check word based on incoming data and generating a second check word based on stored data. The method includes comparing the first check word to the second check word, generating a comparison result, and indicating a failure based on the comparison result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.