Decoding architecture for low density parity check codes
US7246304B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2002 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Mar 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0054
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Architectures for decoding low density parity check codes permit varying degrees of hardware sharing to balance throughput, power consumption and area requirements. The LDPC decoding architectures may be useful in a variety of communication systems in which throughput, power consumption, and area are significant concerns. The decoding architectures implement an approximation of the standard message passing algorithm used for LDPC decoding, thereby reducing computational complexity. Instead of a fully parallel structure, this approximation permits at least a portion of the message passing structure between check and bit nodes to be implemented in a block-serial mode, providing reduced area without substantial added latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.