Topological analysis based method for identifying state nodes in a sequential digital circuit at the transistor level
US7246334B1 · kind B1 · utility
4Cited by
1References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2005 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Jan 7, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
State nodes in a sequential digital circuit are identified using a graph-based method based upon the topology of the circuit. In accordance with the method, the device level circuit netlist is reduced to a graph representation using a well-defined set of rules. The unique properties of state nodes can be translated to properties of the graph representation of the circuit. Identification of state nodes is required for proper initialization of sequential circuits for simulation by a device level digital simulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.