Self adjusting transfer gate APS
US7247898B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 4, 2005 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jul 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/803
Abstract
An active pixel sensor circuit comprising a photodiode, a storage node, and a transfer gate between the photodiode and storage node, where the potential barrier between the photodiode and the storage region is maintained during charge accumulation, thereby preventing charge tunneling between the photodiode and the storage region. This is achieved by electrically connecting the transfer gate, which controls charge transfer between the photodiode and the storage region, to the storage region. Connecting the transfer gate to the storage region maintains the potential barrier between the photodiode and the storage region at a threshold voltage during the charge integration period which prevents charge tunneling between the photodiode and the storage node. The threshold voltage is determined by the implant levels used to form the active pixel sensor and can be optimized by using optimum implant levels. This prevention of charge tunneling between the photodiode and the storage node eliminates image lag.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.