Differential buffer circuit with reduced output common mode variation
US7248079B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2005 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jan 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0276
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal. The buffer circuit further includes a common mode detection circuit and a common mode control circuit. The common mode detection circuit is operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage. The common mode control circuit includes a first terminal connected to the current source and a second terminal connected to the current sink. The common mode control circuit is operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.