Stacked transistor method and apparatus
US7248120B2 · kind B2 · utility
165Cited by
16References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2004 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jun 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/61
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is described for controlling conduction between two nodes of an integrated circuit via a stack of FETs of common polarity, coupled in series. In an RF Power Amplifier (PA) having appropriate output filtering, or in a quad mixer, stacks of two or more FETs may be used to permit the use of increased voltages between the two nodes. Power control for such RF PAs may be effected by varying a bias voltage to one or more FETs of the stack. Stacks of three or more FETs may be employed to control conduction between any two nodes of an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.