Adjusting subline address for burst transfer to/from computer memory
US7248380B1 · kind B1 · utility
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8Claims
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Key dates
| Filing date | Dec 18, 1992 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Dec 18, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A burst-mode data transfer arrangement for transferring a “LINE” of data, arranged in a four-subline array, between a 32-bit-subline memory and a cache memory having 64 bits per sub-line, where, in every such transfer, four sublines must be transferred successively in one of four different sequences, depending on whether the initial access-subline is subline-#1, -#2, -#3 or -#4; this arrangement being adapted to derive the address of the third subline by:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.