Data retention in a semiconductor memory
US7248508B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2006 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jan 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The application discloses a semiconductor memory storage device comprising: a data retention portion comprising latches; a peripheral portion comprising read and write logic; and a power switching device wherein said peripheral portion is operable to be powered by a periphery voltage difference; said data retention portion is operable to be powered by a data retention voltage difference said data retention voltage difference being different to said periphery voltage difference; and in response to a write request signal to write to at least one of said latches output from said peripheral portion to said data retention portion by said write logic, said power switching device is operable to reduce a voltage difference across said at least one of said latches such that a data signal output from said peripheral portion and having a voltage level determined by said periphery voltage difference is able to write to said at least one of said latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.