Semiconductor memory devices having negatively biased sub word line scheme and methods of driving the same
US7248535B2 · kind B2 · utility
9Cited by
14References
23Claims
0Family size
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Key dates
| Filing date | Jan 31, 2006 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jan 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory devices having a negatively biased sub-word line scheme and methods of driving the same are disclosed. In a semiconductor memory device, NMOS transistors for pulling down a word line enable signal and a word line driving signal to a negative voltage are adjusted to a negative voltage. The negatively biased word line scheme may decrease influx of discharge current into the negative voltage source and decrease negative voltage fluctuations and associated noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.