Timesliced discrete-time phase locked loop
US7248664B2 · kind B2 · utility
4Cited by
2References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 29, 2003 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jun 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A time-sliced discrete-time Phase Locked Loop which is suitable for simultaneously synchronizing multiple input signals to multiple output signals is provided by implementing a discrete-time phase detector, loop filter, and voltage controlled oscillator that together operate as a single discrete-time PLL in hardware and applying control logic to retrieve the history for each signal pair from a context memory (RAM), to enable the discrete-time PLL hardware, and to store the resulting history in the context memory for use in subsequent operations for a particular input/output signal pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.