Internal data bus interconnection mechanism utilizing central interconnection module converting data in different alignment domains
US7249207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2005 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jul 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip includes multiple functional components and a central interconnect (CI) module. Each functional component communicates with the CI module via a respective internal bus sharing a common architecture which does not dictate any particular data alignment. The chip architecture defines an alignment mechanism within the CI module, which performs any required alignment of transmitted data. Alignment mechanism design parameters can be varied to accommodate different alignment domains of different functional components. Preferably, the common bus architecture supports multiple internal bus widths, the CI module performing any required bus width conversion. Preferably, for certain transactions not containing a data address, correct alignment is obtained by placing restrictions on transaction size and boundaries, and duplicating certain data on different alignment boundaries. The use of a common bus protocol and CI module having alignment capability streamlines the design process and reduces the overhead of alignment conversion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.