Method for performing performance optimization operations for a processor having a plurality of processor cores in response to a stall condition
US7249268B2 · kind B2 · utility
41Cited by
7References
11Claims
0Family size
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Inventor
Key dates
| Filing date | Jun 29, 2004 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Sep 7, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method to make the most use possible of available capacities for the supply of power to and/or the dissipation of heat from a plurality of processor cores through responding to stalls in one or more of the processor cores among the plurality of processor cores by placing stalled processor cores into a lower power state and increasing the voltage and/or power of the remaining processor cores, and by decreasing the voltage and/or power of the remaining processor cores and taking stalled processor cores out of a lower power state when a condition causing a stall has ceased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.