System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity
US7249306B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 20, 2004 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jul 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A System and Method for generating Cyclic Redundancy Check (CRC) values in a system adapted simultaneously handling a plurality of blocks in parallel is described. Included is a memory or other storage device for storing data blocks, wherein the memory or storage device is adapted to output a plurality of data blocks in parallel. A data bus provides a data path wide enough to accommodate the parallel data blocks and is further coupled to a plurality of CRC cores coupled to the data bus, wherein CRC values are calculated for every combination of data blocks on the data bus. A multiplexer coupled to the CRC cores selects the output of one of the CRC cores based on the number of valid data blocks on the data bus. Once the correct CRC value has been calculated, it is appended to a data segment, comprised of a group of data blocks, for transmission to another device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.