Single-burst-correction / double-burst-detection error code
US7249309B2 · kind B2 · utility
26Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2003 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jan 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/17
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing encoding and decoding of bit chain data packets conveying errors which do not spread on more than n bits, at very high speed. In one embodiment, a matrix of the corresponding Systematic code is built using p×p matrix blocks comprising elements of a galois field, generated by an irreducible generator polynomial of degree p, p being greater or equal to n.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.