Method for optimizing high frequency performance of via structures
US7249337B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2003 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Apr 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/163
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) or backplane is provided. According to one embodiment of the present invention, the method involves the use of S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias within the PCB or backplane. In certain embodiments, the process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.