Synthesis of cyclic combinational circuits
US7249341B2 · kind B2 · utility
1Cited by
4References
69Claims
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Key dates
| Filing date | Dec 5, 2003 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Oct 31, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for the synthesis of multi-level combinational circuits with cyclic topologies. The techniques, applicable in logic synthesis, and in particular in the structuring phase of logic synthesis, optimize a multi-level description, introducing feedback and potentially optimizing the network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.