Low inductance multilayer capacitor
US7251116B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Jul 14, 2006 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Jul 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G4/30
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multilayer parallel plate capacitor with an extremely low inductance comprises a generally rectangular parallelepiped that includes at least one pair of generally rectangular consecutive composite layers stacked parallel to each other in the vertical direction, each composite layer of the pair comprising a dielectric substrate and a conductor plate thereon. Each conductor plate includes two or more lead portions to enable connection to terminal electrodes, and plates on consecutive composite layers are connected to terminal electrodes of opposite polarity. Each conductor plate advantageously includes one or more non-conductive regions comprising slots in the transverse direction, and one or more non-conductive regions comprising slots in the longitudinal direction. These slots provide directionality to the electrical currents through the plates, resulting in a capacitor structure with greatly reduced inductance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.