System for clock and data recovery
US7251296B2 · kind B2 · utility
3Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2002 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | May 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0332
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery (CDR) system that generates one or more clock signals from a received data stream and determines an optimal clock signal to associate with the incoming data stream. The system includes a candidate clock generation circuit that operates to receive the incoming data stream and generate candidate clock signals. A transition density detector circuit determines a transition density parameter associated with each of the candidate clock signals. A controller operates to determine the optimal clock signal based on the transition density parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.