Time delay estimator
US7251299B2 · kind B2 · utility
0Cited by
8References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2003 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Jun 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/23
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system for time delay estimation in a discrete time processing system includes a cross correlator that performs cross correlation on a first signal and a second signal, and provides a cross correlated output signals indicative thereof. A lag smoother receives the cross correlated output signals, and provides lag smoothed output signals indicative thereof. A select logic module selects a pre-defined number of signal values from a respective set indicative of the lag smoothed output signals to compute the time delay estimation associated with the first and second signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.