System and method for sequencing multiple write state machines
US7251739B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 31, 2003 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Apr 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, systems and methods for sequencing multiple write state machines may comprise a pulse generator, a delay circuit, and a stacked memory array, wherein each memory array in the stacked memory array have an individual write state machine. In an exemplary embodiment, the pulse generator may be operable to supply pulses of current to the write state machines so that the system's voltage regulator may accommodate the total aggregated current in the system. In some exemplary embodiments, pulses of current may be applied to the first write machine, and delayed pulses of current may be applied to the second write state machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.