Autonomous fail-over to hot-spare processor using SMI
US7251746B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2004 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Jun 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for dynamically replacing a failing processor in a server system configured with IA-32 architecture without requiring hardware changes to the IA-32 architecture or administrative effort. At least one processor of the multiprocessor system (MP) is initially provided as a reserve (or hot-spare) processor that remains in an idle, off, or low-power mode. While in that mode, the OS is prevented from initially utilizing the hot-spare processor. When a processor failure is detected, SMI code running on a good processor instructs the OS to hold off allocating processes to the failing processor. Contemporaneously, the SMI (and OS) activates and completes an initialization of the hot-spare processor to prepare it to begin receiving the held-off processes. Control is then returned to the OS, which updates the “active” processor list and allocates the threads that were running on the failing processor to the hot-spare processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.