Apparatus and method for maintaining data integrity following parity error detection
US7251755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2004 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Jul 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/079
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine is invoked to perform parity error recovery according to stored transaction information regarding an error bus transaction of the detected parity error. In one embodiment, the stored information includes a bus master that caused the error, as well as an address associated with the corrupt data for which the parity error was asserted. In one embodiment, data logging is performed to track the bus masters associated with error bus transactions to enable identification of problematic or old hardware devices. Other embodiments are described and claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.