Simulation testing of digital logic circuit designs
US7251794B2 · kind B2 · utility
26Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Oct 21, 2004 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Jul 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified simulation model of the simulation model by inserting random skew between an output of each source latch and an input of the logic function only in asynchronous data paths between the source latches and the destination latches of the simulation model; and running the modified simulation model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.