Controlling compatibility levels of binary translations between instruction set architectures
US7251811B2 · kind B2 · utility
31Cited by
21References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2002 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Jun 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method includes receiving a binary of a program code. The binary is based on a first instruction set architecture. The method also includes translating the binary, wherein the translated binary is based on a combination of the first instruction set architecture and a second instruction set architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.