Guard ring for improved matching
US7253012B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2004 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Aug 4, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/95
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain aspects, two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices. A plurality of guard rings may be used that enclose respective arrays of matched devices arranged over the surface of a semiconductor wafer. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, local and global matching are achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.