Molding technique for fabrication of optoelectronic devices
US7253017B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2002 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Jul 10, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/549
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Charge splitting networks for optoelectronic devices may be fabricated using a nanostructured porous film, e.g., of SiO2, as a template. The porous film may be fabricated using surfactant temptation techniques. Any of a variety of semiconducting materials including semiconducting metals and metal oxides (such as TiO2, CdSe, CdS, CdTe, or CuO) may be deposited into the pores of the porous template film. After deposition, the template film may be removed by controlled exposure to acid or base without disrupting the semiconducting material leaving behind a nanoscale network grid. Spaces in the network grid can then be filled with complementary semiconducting material, e.g., a semiconducting polymer or dye to create a exciton-splitting and charge transporting network with superior optoelectronic properties for an optoelectronic devices, particularly photovoltaic devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.