Method of manufacturing CMOS transistor by using SOI substrate
US7253039B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2004 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Feb 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
Abstract
In a method of manufacturing a CMOS transistor, an n-channel MOS transistor is formed on an upper MOS transistor in a first region of an SOI substrate having first and second regions. Next, an insulating layer of the SOI substrate is exposed by removing an upper silicon layer in a second region, and then, a first insulating layer is formed to cover the first and second regions. Next, a silicon epitaxial layer is formed on the first insulating layer of the second region, and then, a p-channel MOS transistor is formed on the silicon epitaxial layer. An n-channel MOS transistor is formed on the upper silicon layer of the SOI substrate and a p-channel MOS transistor on the first insulating layer has a vertical step (relative to the n-channel MOS transistor), so that it is possible to increase integration degree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.