Process for assembling three-dimensional systems on a chip and structure thus obtained
US7253091B2 · kind B2 · utility
72Cited by
45References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Sep 26, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/928
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for assembling an electronic system with a plurality of layers. Recesses in formed in one or more dielectric layers and electronic components are positioned within the recesses. One or more layers containing the components are placed on a host substrate containing host circuits. Electrical interconnects are provided between and among the electronic components in the dielectric layers and the host circuits. The layers containing the components may also be provided by growing the electronic devices on a growth substrate. The growth substrate is then removed after the layer is attached to the host substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.