Self-aligned method for defining a semiconductor gate oxide in high voltage device area
US7253114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2005 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Jul 6, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/942
Abstract
A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit device. A dry etching operation is used to remove the relatively thick gate oxide from the high voltage area using photoresist masking of the low voltage area and a hard mask in the high voltage area, to mask the gate oxide films. A wet etching procedure is then used to remove the gate oxide film from the low voltage areas. The hard mask may be formed over a polysilicon structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.