Snapshot CMOS image sensor with high shutter rejection ratio
US7253461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2005 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Aug 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8057
Abstract
A pixel image sensor has an isolation barrier and diffusion well connected to a biasing voltage to prevent substrate charge leakage caused by photoelectrons generated in the substrate beneath a photon sensing area of the pixel image sensor from drifting to a storage node. An opaque metallic silicide layer is deposited on and a metal shield is fabricated above the storage node and storage node control transistor switches to prevent light from impinging on the storage node and storage node control transistor switches and thus preventing generation of photoelectrons at the storage node and storage node control transistor switches. A guard ring surrounds the photo sensing area, the storage node, and the storage node control transistor switches and is in contact with the biasing voltage and reduces cross-talk from photoelectrons drifting from adjacent image sensors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.