Output clock phase-alignment circuit
US7253674B1 · kind B1 · utility
1Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2005 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Aug 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock generator has a reset circuit and (at least) two dividers, where each divider divides a reference clock signal by a divisor value to generate an output clock signal. The reset circuit generates reset signals for the dividers, where the reset signals are delayed relative to one another by a selected number of reference clock cycles, such that the dividers generate output clock signals having a desired phase offset between them.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.