Clamping circuit for operational amplifiers
US7253687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2005 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Dec 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45636
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential input operational amplifier has a voltage clamp differential transistor pair coupled to an input differential transistor pair of the operational amplifier. The voltage clamp differential transistor pair limits the output voltage of the operational amplifier by taking over control of the operational amplifier circuits from the input differential transistor pair as the output voltage approaches a clamp voltage value. A reference voltage may be used to set the output voltage at which the input differential transistor pair will be clamped by the voltage clamp differential transistor pair. Below the clamp voltage, operation of the input differential transistor pair will not be affected. At the clamp voltage the input differential transistor pair will no longer control the output of the differential amplifier, rather the voltage clamp differential transistor pair will control the maximum voltage output of the differential amplifier. Both positive and negative limiting of the operational amplifier output voltage may be accomplished.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.