Data form converter between serial and parallel
US7253754B2 · kind B2 · utility
12Cited by
10References
14Claims
0Family size
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Key dates
| Filing date | May 10, 2004 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Aug 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data form converter allowing parallel-to-serial or serial-to-parallel conversion at various conversion ratios is disclosed. A frequency divider divides an input clock in frequency at a variable frequency division ratio to produce a single frequency-divided clock. A data shift circuit shifts serial input data according to the input clock to output n-bit parallel data, where n is determined depending on the variable frequency division ratio. A retiring section synchronizes the n-bit parallel data with the single frequency-divided clock to output parallel output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.