Digitally adjusted high speed analog equalizer
US7254173B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2003 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Apr 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0292
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high speed CMOS-implemented equalizer architecture as described herein utilizes a digitally controlled analog equalization scheme to equalize intersymbol interference present in an input signal. The equalizer structure includes an inductor high frequency gain boosting stage and a feed forward high frequency equalizer stage connected in series. The equalization performed by each of these gain boosting stages is controlled by one or more digital control signals. The combination of these stages results in the equalization of both amplitude and phase distortion. The equalizer architecture is suitable for use with communication systems that operate at 11.2 Gbps speeds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.