On-chip inter-network performance optimization using configurable performance parameters
US7254603B2 · kind B2 · utility
13Cited by
30References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2002 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Oct 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/46
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for on-chip inter-network performance optimization using configurable performance parameters have been described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.