Dual mode capability for system bus
US7254657B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2005 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Nov 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system with a mode-selectable bus interface. In one embodiment, the computing system includes a system bus, a processor coupled to the bus via an interface unit, and a controller coupled to the bus. The system bus implements one of a first and a second system bus protocols. The interface unit is compatible with the first system bus protocol in a first selectable mode and the second system bus protocol in a second selectable mode, and the controller is compatible with one of the system bus protocols. A mode register is coupled to the interface unit, and the interface unit selects the first mode responsive to a first value of the mode register and selects the second mode responsive to a second value of the mode register. A scan controller is coupled to the mode register for scanning a value into the mode register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.