Security supervisor governing allowed transactions on a system bus
US7254716B1 · kind B1 · utility
10Cited by
19References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Mar 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit generally comprising a plurality of master modules and a supervisor module is disclosed. The supervisor module may be configured to (i) detect a target address and a particular master module of the master modules initiating a transaction on a bus, (ii) identify a predetermined authorization in response to the particular master module, the target address and a current security mode of at least three security modes and (iii) subvert the transaction in response to the predetermined authorization restricting the transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.