Precise exit logic for removal of security overlay of instruction space
US7254720B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Mar 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit generally comprising a first memory, a processor and a logic block is disclosed. The first memory may store (i) a write instruction to store a non-highest security value of at least three security values in a register and (ii) a jump instruction to a second memory. The processor may have a pipeline and may be configured to (i) bootstrap to the first memory while the register stores a highest security value of the security values and (ii) execute the jump instruction following the write instruction. The logic block may be configured to (i) detect the write instruction in an execution stage of the pipeline and (ii) store the non-highest security value in the register in response to detecting the write instruction in a write back stage of the pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.