On-chip receiver sensitivity test mechanism
US7254755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2004 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Mar 30, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2822
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillator, to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated. The BER reading is used either externally or by an on-chip processor or controller to establish a pass/fail indication for the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.