Phase-locked loops
US7256629B2 · kind B2 · utility
6Cited by
10References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2006 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Mar 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/187
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module further configured to multiply the control signal by a square root of the state information to provide a tuning signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.