Phase-locked loop apparatus and method thereof
US7256655B2 · kind B2 · utility
4Cited by
0References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2005 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Dec 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL device includes a first hybrid PLL and a second digital phase/frequency detection module. The second digital phase/frequency detection module and the first hybrid PLL's oscillator, switching unit, and analog control signal generating module are capable of forming a second hybrid PLL. The switching unit selectively activates either the first hybrid PLL or the second hybrid PLL according to a selection signal to generate an analog control signal with the analog control signal generating module for controlling the oscillator, in order to control the frequency of a clock signal generated by the oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.