Memory circuit and related method for integrating pre-decoding and selective pre-charging
US7257041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2006 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Mar 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory circuit, memory cells are arranged in a matrix by “row line-and column line” (may also denoted as “word line and bit line”). The invention provides a memory circuit and related method capable for independently pre-charging the column lines or bit lines selectively during data accessing according to results of column pre-decoding to decrease the pre-charging power consumption. After pre-charging, the objective memory cell is enabled to change or not to change the corresponding electric level of the connected column line according to the stored data, and a sense amplifier detects the stored data by measuring the electric level of the column line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.