Data memory address generation for time-slot interchange switches
US7257115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2002 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Dec 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Time-slot interchange (TSI) switches and a pipelined data memory address generation circuit are provided. The TSI switches and the pipelined data memory address generation circuit include a first pipeline stage that reads data from a connection memory. A second pipeline stage compares the data read from the connection memory to provide a bank selection value. Optionally, a third pipeline stage reads data from a data memory based on the bank selection value and the data read from connection memory. The timing of the pipeline stages may be adjusted such that the duration of the first pipeline stage is extended and the duration of the second pipeline stage shortened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.