Encoding viterbi error states into single chip sequences
US7257147B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Apr 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J13/0022
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A technique for receiving an error state in a single chip sequence in a wireless communications network is disclosed. The error state may comprise a Viterbi error state. The error state may be identified as a target code encoded in the single chip sequence, the target code comprising either a code or the complement of the code. The code may comprise a PN-Code. The error state may be identified using a previous mapping of error states from a set of error states to a group of codes, the group of codes comprising a plurality of codes and their complements. The error states in the set of error states in the previous mapping may be uniquely mapped to plurality of codes and their complements in the group of codes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.